The present invention is directed to a method and system for computing delay and crosstalk on lossy transmission-lines with improved efficiency and accuracy.
Continued progress in integration levels is making possible the fabrication of large and complex microprocessor chips close to 10 million transistors. Such large dies (close to 20 mm on a side), incorporate a major portion of the system that used to be spread on several chips. Operating clock frequencies are shortly approaching GHz rates with typical signal transitions of 25-50 ps. Critical interconnects such as clock lines, control lines, and data lines between processor and cache can be 1-2 cm in length. The performance of on-chip wiring is becoming a dominant factor in the performance of future systems.
Transmission-line properties of on-chip interconnections need to be taken into account due to the long lengths and fast risetimes. The traditional lumped-circuit or even distributed RC representation is no longer adequate, since it results in substantial under-estimation of both crosstalk and delay. On-chip transmission lines have unique characteristics namely, very high capacitive and inductive coupling and resistive losses, and very non-uniform structures.
Although the global interconnects represent a small percentage of the total wiring demand, delay on such critical paths is determining the system cycle time. Crosstalk on fast switching wide data busses can create logic failure. Today a typical chip might have only 10-20K global nets of interest but this number will shortly climb to more than 100k connections. Three-dimensional RLC matrix extraction is not generally done because it is computationally too expensive. One such set of two-coupled transmission lines requires 60 hours of computation on an IBM RS/6000 model 590 in order to obtain the frequency-dependant RLC(f) matrix. A distributed RC-circuit representation can underestimate delay by 20-40% while constant-parameter RLC circuit can over predict crosstalk by as much as 20-40% compared to the RLC(f) case.
Typical wire routers have only length delay restrictions. Post-routing analysis is generally done on a per-net basis. This analysis involves two-dimensional or some limited three-dimensional extraction and signal propagation delay and crosstalk simulation with subsequent rerouting or circuit design changes. Both delay and crosstalk evaluations do not include inductance or inductive coupling. Often times empirical analytical formulations are used with high degree of inaccuracy. Accurate delay prediction is most critical for the clock lines that need to feed thousands of circuits with equal delay or minimum skew.
Crosstalk evaluation is a multi-variable problem that requires waveform simulation since it depends on parameters such as wiring dimensions, driver and receiver circuit size, coupled length, circuit topology (near-end or far-end coupling), interlayer interactions. The non-uniform current return path for the on-chip transmission lines results in frequency-dependent current distribution in the reference conductors (Vdd and GND) with subsequent increase in crosstalk. This frequency-dependence differs for each wiring layer depending on the relative position of the signal lines to the nearest or least resistive power conductors (parallel or orthogonal). Thus each layer in a 5-6 layer stack has to be analyzed differently. A signal path, however, could start on layer M6 and then continue on M4 and M2 as shown in FIG. 1. FIG. 7 Table shows the calculated R(f) and L(f) matrices for two-adjacent lines in layer M6 and M5. The largest variation with frequency is exhibited by the R12(f) terms which represent the current return path resistance in the reference conductors. The L11(f) and L12(f) terms show much lower rate of change due to the presence of the parallel near-by, in-plane (or two layers away) power conductors.
It is possible then to consider these lines as consisting of a concatenation of lines, each piece being in a different layer. A model can be generated for each layer. The inductive and resistive current return path can be defined within a regional radius as shown in FIG. 2. Moreover, the strongest coupling is generally found to the closest neighbor such that multi-coupled lines can be analyzed as pairs only and crosstalk summed by linear superposition. Finally, due to the very high resistive losses, most circuit simulators have numerical stability problems with the on-chip coupled transmission-lines. Such coupled-lossy lines can be represented by a distributed network consisting of a cascade of lumped-element xcfx80-section RLC network. This network then synthesizes the R(f) and L(f) that are calculated with the three-dimensional extractor. It provides a close approximation to the series impedance and shunt admittance over a frequency range of interest. The synthesized network can use either a Foster or Cauer-type low-pass filter topology built out of lumped linear elements (R,L,and C""s) that can easily be implemented in standard CAD tools. The R""s and L""s can be obtained from two-dimensional (2D) calculations and scaled by predetermined constants to obtain the equivalent R""s and L""s from three-dimensional shape calculations, thus considerably reducing computation time.
This invention presents a technique for reducing the complexity and improve accuracy of calculation for delay and crosstalk for on-chip interconnections. This method allows a fast frequency-dependent analysis that can be performed for tens of thousands of nets in minutes (1 minute"" per net instead of 60 hours per net). The invention uses an analysis tool that relies on pre-calculated RLC matrices, synthesized circuits and device models, all stored in large tables. Based on the net topology obtained from actual product chip layout, the tool transfers the data from these tables into a circuit simulator, evaluates delay and cross-talk and determines performance or design changes needed for the final product. Design cycle for bringing a micro-processor chip to market is thus greatly reduced.